Self calibrating digital delay-locked loop

Details Self calibrating digital delay-locked loop Self calibrating digital delay-locked loop

2002-12-03

2004-01-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

06680634

ABSTRACT:

TECHNICAL FIELD
These teachings relate generally to clock frequency generators and, more specifically, relate to clock frequency generators that employ digital delay-locked loop (DLL) circuitry.
BACKGROUND
The evolution of radio frequency (RF) and baseband (BB) circuit architectures in wireless communication terminals and devices, and the increasing trend toward high levels of integration of these and related circuits (e.g., so-called “radio on a chip” architectures), is placing more challenging requirements on local clock generation and RF up and down frequency conversion. In general, however, these problems are shared by all electronic devices that require frequency multiplication and/or multi-phase clock generation.
The DLL overcomes certain problems typically found in the conventional phase-locked loop (PLL), such as stability and jitter problems related to accumulated jitter induced by the power supply and reference clock. In that the timing uncertainties occur only within the period of the reference clock (shown as T
REF
in FIG.
1
B), the DLL is capable of generating multi-phase clock signals that exhibit very low jitter. Additionally, DLLs are first order systems, which provides some advantages as compared to higher order PLLs, e.g., DLLs are more stable and do not require large off-chip components, such as capacitors, to implement the second order loop filter.
FIG. 1A
illustrates the conventional structure of a DLL (see, for example, Chien G. & Gray P. R. (2000) A 900-MHz Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications. IEEE Journal of Solid-State Circuits, vol. 35, pgs. 1996-1999). The basic DLL
1
contains an adjustable delay line
2
, a feedback loop
3
and a clock edge combiner, more simply an edge combiner
4
. A reference clock generator
5
feeds a reference clock signal R
REF
to a first element of the delay line
2
, and the output of the last element of the delay line
2
is fed to a phase detector of the feedback loop
3
. The feedback loop
3
compares the phase difference of the output of the last delay line element to the reference clock and adjusts the delay line
2
to lock-on to reference clock signal. When the loop is locked, the total delay of the delay line
2
is equal to the period of the reference clock signal. The implementation of the feedback loop
3
can be analog or digital. The function of the edge combiner
4
, which receives inputs from the outputs of individual ones of the delay line elements, is to decode the outputs of the delay line elements to generate the output clock signal F
OUT
. The operation of the clock edge combiner
4
is shown in
FIG. 1B
(see again, for example, G. Chien et al., supra).
One basic shortcoming of the conventional DLL
1
is that it suffers from problems caused by a mismatch between the elements of the delay line
2
. For example, an integrated circuit (IC) implementation can result in the existence of small differences between the elements. This mismatch can result in a periodic jitter on the output clock signal F
OUT
, and thus generates undesirable spurious tones in the output signal. A most disadvantageous spurious tone occurs at a frequency that is offset by (plus and minus) F
ref
from the output frequency F
OUT
, as shown in the exemplary spectrum of
FIG. 2
, which shows the spectrum of a three times multiplied clock and assumes a 10% delay line element mismatch. The spurious tones that occurs at a frequency that is F
ref
away from the output frequency F
OUT
may fall within the signal band of interest, and thus represent an internally generated noise source.
Prior approaches to correcting this problem include attempting to match the elements of the delay line
2
as closely as possible, which adds cost, and selecting the ratio of the reference frequency and output frequency so that the generated spurious tones are not located in the signal band of interest, which adds complexity and places constraints on circuit operational parameters.
It should be noted that although much effort can be expended on designing and fabricating identical delay line elements, there is always some residual mismatch due to IC process variations and gradients.
SUMMARY OF THE PREFERRED EMBODIMENTS
The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings.
In accordance with this invention the delay of the entire delay loop is calibrated with a main digital adjustment that affects all of the delay elements, in combination with individual digital adjustment that is used to calibrate the delays of each individual delay element.
In accordance with an aspect of this invention, a solution to the mismatch problem is to provide the delay line with an additional delay element. The delay line calibration is performed by circulating the starting and ending point of the delay line, and individually adjusting the delays of the individual delay elements. After being calibrated the delay line has delay elements with (ideally) identical unit delay, and spurious tones can thus be eliminated.
The inventors have realized that this technique is most optimally applied to the case where a division is made between a common, main calibration component and a plurality of fine, individual calibration components, and by the use of digital control techniques and digital storage of the control quantity used with a cyclically operated delay line. This is true at least for the reason that implementing this type of calibration with an analog feedback loop is not the most optimum approach, as the delay adjustment procedure requires implementing, for each delay line element, a relatively large capacitor to store a local bias voltage.
In the preferred embodiment of this invention a DLL calibration architecture with multilevel digital delay control is provided. In a presently preferred, but non-limiting embodiment each delay element is provided with a digital to analog converter (DAC), referred to as a fine adjustment DAC, or more simple as a fine DAC, that functions to adjust the differences between delay line elements. The entire delay line is forced to lock-on to the reference clock using a main DAC having an output that is input as a common bias signal to all of the delay line elements.
Calibration can be continuous during operation of the delay line or loop, or it may occur only during predetermined calibration periods.
This invention aids in eliminating spurious tones and deterministic jitter in clock signals generated by the DLL, thereby improving the operation of, for example, ADC sampling and RF-up-conversion and down-conversion circuitry.
Disclosed is a method for operating and calibrating a delay-locked loop containing a chain of delay line elements that propagate a reference clock from delay line element to delay line element. Also disclosed is a delay-locked loop that operates in accordance with the method. The method includes, during a calibration procedure, sequentially varying the configuration of the chain of delay line elements so that there is one unused delay line element and a plurality of used delay line elements and, for each configuration, electrically compensating at least one delay line element based on a phase comparison results obtained from previous calibration configurations of the delay line elements so as to set the total delay through the chain of delay line elements at a desired value. The phase comparison is made between the reference clock and the propagated reference clock. Varying the configuration of the chain of delay line elements is accomplished in the preferred embodiment by changing the start and end of the chain of delay line elements.
In one embodiment the step of electrically compensating is an immediate compensation that occurs after each phase comparison and electrically compensates all of the used delay line elements. In another embodiment the step of electrically compensating is a cyclic compensation that occurs after each phase comparison, and that electrically compen

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