Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-02-17
2001-07-10
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S298000, C327S115000, C377S016000
Reexamination Certificate
active
06259291
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an apparatus and a method for adjusting clock signals, and more particularly, to a self-adjusting apparatus and a self-adjusting method for adjusting an internal oscillating clock signal by using the self-adjusting apparatus.
2. Description of Related Art
A clock generator is normally included in the design of an electronic circuit for generating clock signals to control the sequence of signal and data processing and to synchronize different signals in order to prevent the occurrence of malfunction caused by disordered signal processing sequence. In most electronic circuits, the clock signal generated by a clock generator is often used as a trigger for activating a process and resetting a process. In some situations, the clock signals also serve as a reference signal.
According to the current designing demand, a clock generator has become a required component of an electronic circuit that includes integrated circuits (ICs), so that the ICs can operate in various power-consuming modes, such as normal mode and power-down mode, depending on the actual needs for energy-saving purposes. Conventionally, a clock generator includes a crystal and an oscillator. It is designed to be external to an IC, and to be connected to the IC by an electronic circuit. However, since the power supply to the clock generator is independent from that to the IC, the power distribution of the electronic circuit becomes more complicated. Furthermore, the power supply to the clock generator alone has become a drain of system power even while the IC is running in a power-down mode.
Another conventional design of an electronic circuit including an IC and a clock generator forms the clock generator inside the IC in order to make the device more energy-conservative. The built-in clock generator is normally formed by implementing a logic device fabrication process into the fabrication process of the IC. However, the clock generator made with a logic device fabrication process alone can hardly provide a very precise internal clock signal; therefore, some extra processes are required to ensure that the clock signal generating frequency is acceptable. In addition, the clock generator is non-adjustable once it is made. As a result, the IC is useless if the built-in clock generator cannot generate a clock signal in a precise frequency.
In view of the foregoing, there is a need for a self-adjusting apparatus and method that is able to adjust the internal oscillating clock signal while the device is running in a normal mode accordingly to an external clock signal.
SUMMARY OF THE INVENTION
The invention provides a self-adjusting apparatus including an internal clock generator built into an integrated circuit (IC), and a method for adjusting the internal clock signal of the IC by using the self-adjusting apparatus to ensure that the IC operates properly in a power-down mode and reduce the power consumption.
In accordance with the foregoing, the invention provides a self-adjusting apparatus including a clock generator built within an IC to generate an adjusted internal oscillating clock signal by referring to an external target signal while the electronic circuit is running in a normal mode. The invention also provides a method for adjusting the internal clock signal of an IC.
While an IC is operating in a normal mode, which consumes more power, the apparatus adjusts the internal oscillating clock signal of the IC by referring to the frequency of an external clock signal generated by an external clock generator. As soon as the IC is forced to run in a power-down mode, which consumes less power, the self-adjusting apparatus is still able to provide a precise internal clock signal required for operating the electronic circuit without the presence of an external clock signal.
The self-adjusting method of the invention adjusts the internal clock signal generated by an internal clock generator built in an IC included in an electronic circuit. The electronic circuit also contains a clock generator external to the IC for generating an external clock signal and a subcircuit for generating a desired external divisor signal. While the electronic circuit is running in a normal mode, the external clock signal is first divided by the external divisor signal for out putting a first target clock signal, which is the external target clock signal. Since the external clock signal and the external divisor signal are normally more precise and reliable, the first target clock signal, which normally can be obtained by using a divider, is then used as a reference signal for stabilizing and adjusting the internal clock signal. By using a counter to count the number of periods of the internal clock signal occurring within one period of the external target clock signal, an internal divisor signal is obtained. Then, the internal clock signal is divided by the internal divisor signal for obtaining a second target signal, which is the internal target signal. The frequencies of the first target clock signal and the second target clock signal are the same. Therefore, as soon as the IC is forced to run in a power-down mode, the operation of the IC can still operate properly by using the second target clock signal as a stable and reliable reference signal.
The invention provides a self-adjusting apparatus for adjusting an internal clock signal to generate an internal target clock signal by referring to a provided external clock signal and a provided divisor signal while the IC is running in a normal mode. The internal oscillating clock signal is then employed in the absence of the external clock signal when the IC is running in a power-down mode. The self-adjusting apparatus of the invention contains a clock generator, a first clock divider, a counter and a second clock divider. The first clock divider receives both the external clock signal and the external divisor signal, and outputs an external target clock signal by dividing the external clock signal by the external divisor. The external target clock signal is then into the counter. In the meantime, an internal clock signal generated by the clock generator is also fed into the counter. The counter generates an internal divisor signal by counting the number of periods of the internal clock signal occurring within one period of the external target clock signal. The internal divisor signal is subsequently sent to the second clock divider. The second clock divider also receives the internal clock signal from the clock generator of the self-adjusting apparatus. By dividing the internal clock signal with the internal divisor signal, the second clock divider then output the internal target clock signal, which is an adjusted internal clock signal. Because the internal target clock signal is actually obtained by referring to the external clock signal and the external divisor signal, the frequency of the internal target clock signal is equal to the frequency of the external target clock signal. Hence, the frequency of the internal oscillating clock signal is adjusted, and can be used by the IC in the absence of the external clock signal.
The invention also provides another self-adjusting apparatus for adjusting the internal clock signal of an IC. The self-adjusting apparatus is capable of generating an adjusted internal oscillating clock signal, an internal target clock signal, by referring to a provided external clock signal and a provided external divisor signal. The self-adjusting apparatus contains a clock generator, a first clock divider, a counter, a second clock divider and a buffer. The first clock divider receives an external clock signal and an external divisor signal, and outputs an external target clock signal by dividing the external clock signal with the external divisor signal. The external target clock signal is fed into the counter. In the meantime, an internal clock signal generated by the clock generator is also fed into the counter. The counter obtains an internal divisor signal by counting the number of perio
Cox Cassandra
Integrated Technology Express Inc.
Knobbe Martens Olson & Bear LLP
Tran Toan
LandOfFree
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