Sampled delay locked loop insensitive to clock duty cycle

Details Sampled delay locked loop insensitive to clock duty cycle Sampled delay locked loop insensitive to clock duty cycle

1998-07-09

2000-11-14

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327147, 327263, H03L 706

Patent

active

061475319

ABSTRACT:
A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

REFERENCES:
patent: 4338569 (1982-07-01), Petrich
patent: 5220206 (1993-06-01), Tsang et al.
patent: 5537069 (1996-07-01), Volk
patent: 5574756 (1996-11-01), Jeong
patent: 5663665 (1997-09-01), Wang et al.
patent: 5764092 (1998-06-01), Wada et al.
patent: 5777567 (1998-07-01), Murata et al.
patent: 5880612 (1999-03-01), Kim
patent: 5883534 (1999-03-01), Kondoh et al.
patent: 5952857 (1999-09-01), Suzuki

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