Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-10-02
2002-05-21
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S012000, C327S141000, C327S023000, C327S231000
Reexamination Certificate
active
06392457
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a clock recovery circuit and, more particularly, to clock recovery circuit comprising a self-aligned proportional phase detector (SAPPD) including an integral frequency detection.
BACKGROUND OF THE INVENTION
Clock recovery circuits are employed within optical and RF receivers to establish synchronization between a locally generated clock and the timing of a bit stream within a received data signal. The local clock, once synchronized to the incoming data signal, is used to control regeneration of the data. In most cases, a phase-locked loop (PLL) circuit is used to provide clock recovery.
A phase locked loop (PLL) is a system that uses feedback to maintain an output signal in a specific phase relationship with a reference signal. PLLs are used in many areas of electronics to control the frequency and/or phase of a signal. These applications include frequency synthesizers, analog and digital modulators and demodulators, and clock recovery circuits.
A typical prior art PLL includes a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector produces an output voltage that is proportional to the phase difference between an input signal and the output of the VCO. The loop filter integrates the output of the phase detector and creates a VCO control signal. The VCO produces an ac output signal having a frequency that is proportional to the VCO control voltage.
With conventional phase locked loops, difficulties are presented when attempting to phase lock to high frequency input signals. For example, the synchronous optical network (SONET) standard specifies that a 622 MHz PLL should have a loop bandwidth of between 250-500 kHz. Unfortunately, a standard PLL can only “pull-in” an input signal that is within about a loop bandwidth of the nominal frequency. In the above example, this means that a SONET standard PLL has a “pull in” range of about ±0.04% to about ±0.08%. Techniques for extending the frequency lock range of a PLL circuit based on sampled phase detectors utilize a square wave as an auxiliary input to initially tune the VCO, while using an additional phase and frequency detector (PFD) to compare the frequency of the auxiliary input to the VCO output. Once the VCO is tuned to the desired frequency in this manner, the additional PFD is switched out of the PLL feedback loop and the sampled phase detector is utilized to phase lock onto the incoming data. However, relying on the presence of an external reference signal (such as a square wave) to extend the frequency lock range may not be practical in many receiver applications where the only received signal is the incoming random data.
A problem exists, however, for a PLL circuit that utilizes a sampled phase detector. Specifically, for large frequency errors, conventional sampled phase detectors are equally likely to generate a positive or negative phase correction signal, regardless of the actual polarity of the frequency error, since the likelihood of sampling before and after a data edge (due to the frequency error) is fifty percent (50%). Thus, it is necessary to ensure that large frequency errors do not occur by extending the frequency lock range of a PLL circuit.
Thus, a need remains in the art for any arrangement for providing the desired frequency detection within a clock recovery circuit utilizing a sampled phase detector without the need for a separate frequency detection circuit.
SUMMARY OF THE INVENTION
The need remaining in the prior art is addressed by the present invention, which relates to a clock recovery circuit and, more particularly, to a clock recovery circuit comprising a self-aligned proportional phase detector (SAPPD) including an integral frequency detection.
In accordance with the present invention, the data sample outputs generated by the SAPPD are used as inputs to a frequency detection circuit. The clock signals are used to form a pair of quadrature clock signals at a subclock frequency of f
1
-f
2
, thus defining four quadrants in a cycle of the subclock frequency. A “cycle slip” is then determined based on the data samples, and the frequency adjusted on an UP/DOWN basis, depending upon in the quadrant in which the cycle slip occurs.
Other and further aspects and features of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.
REFERENCES:
patent: 4575860 (1986-03-01), Scordo
patent: 4902920 (1990-02-01), Wolaver
patent: 5694088 (1997-12-01), Dickson
patent: 5757857 (1998-05-01), Buchwald
patent: 6087902 (2000-07-01), Larson
patent: 6091304 (2000-07-01), Harrer
J.A. Afonso, A.J. Quiterio, D.S. Arantes, “A phase-locked loop with Digital Frenquency comparator for Timing Signal Recovery” National Telecom. Conf. Rec. paper 14.4, 1979.
Koba Wendy W.
Le Dinh T.
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