Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-03-23
2002-05-07
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06384646
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a select signal generating circuit in a semiconductor integrated circuit. More particularly, it relates to a select signal generating circuit, such as a shift register generating select signals for selecting one of plural bus lines or a pipeline processing circuit generating select signals for selecting a word line in a semiconductor memory device, in accordance with a clock signal.
FIG. 1
is a schematic circuit diagram of a first shift register
100
of the prior art. The shift register
100
generates select output signals Q
0
to Q
3
for selecting one of signal lines, such as bus lines, in accordance with complementary clock signals CK and XCK.
FIG. 2
is a timing chart illustrating the operation of the shift register
100
.
The shift register
100
includes a plurality of flip-flops each of which includes a master stage for generating a master output signal and a slave stage for generating a slave output signal. The shift register
100
is provided with a reset signal XR.
At the time power is provided to the shift register
100
, master output signals MQ
0
to MQ
3
, slave output signals SQ
0
to SQ
3
and the select output signals Q
0
-Q
3
are unsettled.
In order to initialize the select output signals Q
0
-Q
3
, when the reset signal XR falls, the clock signal CK falls, and the clock signal XCK rises, the master stage is initialized, and the master output signal MQ
3
rises. Subsequently, the clock signal CK rises, and the clock signal XCK falls. The slave stage and the select output signals Q
0
-Q
3
are initialized, and only the select output signal Q
3
rises. Thereafter, every time the clock signal CK rises, the select output signals Q
0
-Q
3
rise in order.
The select output signals Q
0
-Q
3
are unsettled until the reset signal XR is provided since power on. Therefore, simultaneous selection of a plurality of signal lines may cause a bus conflict. The bus conflict may cause the through current to flow between circuits that are connected together by the signal lines, thus deteriorating the system.
FIG. 3
is a schematic circuit diagram of a second shift register
120
which can reset the select output signals Q
0
-Q
3
based on a power-ON detection signal G of the prior art. The power-ON detection signal G is generated by a power-ON detection circuit
140
shown in FIG.
4
.
FIG. 5
is a timing chart describing the operation of the power-on detection circuit
140
upon power on.
The power-ON detection circuit
140
includes inverter circuits
1
a
to
1
g
connected in series. A low-potential power supply Vss is connected to the input terminal of the first inverter circuit
1
a,
and the output signal of the last inverter circuit
1
g
is provided to a one-shot pulse generating circuit
2
.
A capacitor C
1
is connected between a node A, which locates between the inverter circuits
1
a
and
1
b,
and the low-potential power supply Vss. A capacitor C
3
is connected between a node C, which locates between the inverter circuits
1
c
and
1
d,
and the low-potential power supply Vss. A capacitor C
5
is connected between a node E, which locates between the inverter circuits
1
e
and
1
f,
and the low-potential power supply Vss. A capacitor C
2
is connected between a node B, which locates between the inverter circuits
1
b
and
1
c,
and a high-potential power supply Vcc. A capacitor C
4
is connected between a node D, which locates between the inverter circuits
1
d
and
1
e,
and a high-potential power supply Vcc.
When the supply voltage Vcc gradually rises as the supply voltages Vcc and Vss are given, with the node A kept at the level of the supply voltage Vss by the capacitor C
1
, the capacitor C
1
is charged by the output signal of the inverter circuit
1
a
so that the voltage at the node A rises together with the supply voltage Vcc.
When the supply voltages Vcc and Vss are given, the voltage at the node B rises together with the supply voltage Vcc due to the capacitor C
2
. Thereafter, when the voltage at the node A rises, the output signal of the inverter circuit
1
b
is inverted so that the voltage at the node B falls toward a low level.
When the output signal of the inverter circuit
1
c
is inverted by the dropped voltage at the node B with the node C kept at the level of the supply voltage Vss by the capacitor C
3
, the capacitor C
3
is charged so that the voltage at the node C rises toward a high level.
The voltage at the node D rises together with the supply voltage Vcc due to the capacitor C
4
. Thereafter, when the output signal of the inverter circuit
1
d
is inverted due to an increase in the voltage at the node C, the voltage at the node D falls toward a low level.
When the output signal of the inverter circuit
1
e
is inverted by the dropped voltage at the node D with the node E kept at the level of the supply voltage Vss by the capacitor C
5
, the capacitor C
5
is charged so that the voltage at the node E rises toward a high level.
A node F rises to a high level after a predetermined delay time since power-on of the supply voltage Vcc. The predetermined delay time is determined by the time constant set by ON resistances of the inverter circuits
1
a
-
1
g
and the capacitances C
1
-C
5
and the rising speed of the supply voltage Vcc.
The one-shot pulse generating circuit
2
generates a one-shot pulse signal (the power-ON detection signal G) at a high level for a predetermined time in response to the rising of the node F.
After power on, when the power-ON detection signal G is provided to the shift register
120
prior to the reset signal XR, the master output signals MQ
0
-MQ
3
and the slave output signals SQ
0
-SQ
3
are reset.
As shown in
FIG. 6
, therefore, when the power-ON detection signal G is provided, only the master output signal MQ
3
and the select output signal Q
3
rise, and only the slave output signal SQ
3
falls.
The timing of providing the power-ON detection signal G is determined by the time constant set by ON resistances of the inverter circuits
1
a
-
1
g
and the capacitances C
1
-C
5
and the through rate (rising speed) of the supply voltage Vcc. When the through rate of the supply voltage Vcc is larger than the speed expected at the time of designing the circuit, the power-ON detection signal G is provided to the shift register
120
before the supply voltage Vcc reaches a predetermined level. As a result, the reset operation is not carried out normally. This requires a certain restriction on the power-ON operation. If the power-ON operation lies off the certain restriction, the reset operation fails.
The shift register
120
has transfer gates opened and closed in accordance with the power-ON detection signal G, and charge/discharge circuits connected to the input terminals of latch circuits of the master stage and slave stage. This design inevitably increases the circuit area of the shift register
120
and increases the load capacitance to the latch circuits, thus lowering the operational speed of the shift register
120
.
FIG. 7
is a schematic circuit diagram of a third shift register
160
which can reset the select output signals Q
0
-Q
3
in accordance with a reset signal XR
1
generated based on the power-ON detection signal of the prior art.
The shift register
160
has the same structure as the shift register
100
except that clock signals CK
1
and XCK
1
and the reset signal XR
1
are provided to the shift register
160
.
FIG. 8
is a schematic circuit diagram of a reset signal generating circuit
180
generating the clock signals CK
1
and XCK
1
and the reset signal XR
1
. The generating circuit
180
is provided with the clock signal CK, the reset signal XR and power-ON detection signals G and H. The power-ON detection signals G and H are generated by a power-ON detection circuit
200
shown in FIG.
9
.
FIG. 10
is a timing chart illustrating the operation of the power-ON detection circuit
200
. The power-ON detection circuit
200
includes first and second one-shot pulse circuits
3
a
and
3
b
connected to the node F of t
Cox Cassandra
Wells Kenneth B.
LandOfFree
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