Single event upset hardened latch
Single event upset hardened latch circuit
Single event upset immune register with fast write access
Single phase edge-triggered dual-rail dynamic flip-flop
Single-event effect tolerant latch circuit and flip-flop...
Single-event upset hardened reconfigurable bi-stable CMOS latch
Single-event upset immune flip-flop circuit
Single-phase edge-triggered dual-rail dynamic flip-flop
Single-stage tri-state Schmitt trigger
Single-transistor-clocked flip-flop
Slave-less edge-triggered flip-flop
Soft error rate tolerant latch
Soft latch circuit having sharp-cornered hysteresis characterist
Soft-error rate hardened pulsed latch
Soft-error rate improvement in a latch
Soft-error rate improvement in a latch using low-pass filtering
Soft-error rate improvement in a latch using low-pass filtering
SOI CMOS Schmitt trigger circuits with controllable hysteresis
Split-slave dual-path D flip flop
SR flip flop