Single-event effect tolerant latch circuit and flip-flop...

Details Single-event effect tolerant latch circuit and flip-flop... Single-event effect tolerant latch circuit and flip-flop...

2006-12-12

2009-08-18

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000, C327S212000

Reexamination Certificate

active

07576583

ABSTRACT:
Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

REFERENCES:
patent: 5504703 (1996-04-01), Bansal
patent: 6327176 (2001-12-01), Li et al.
patent: 6683932 (2004-01-01), Wood
patent: 6696873 (2004-02-01), Hazucha et al.
patent: 6696874 (2004-02-01), Wood
patent: 2004/0017237 (2004-01-01), Wood
patent: 60-224319 (1985-11-01), None
patent: 06-006186 (1994-01-01), None

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