I/O tranceiver having a pulsed latch receiver circuit
Iddq-testable uni-directional master-slave
Initial value setting circuit
Input buffer and input-output buffer in full compliance with IDD
Input buffer circuit with hysteresis for noise control
Input buffer with compensation for process variation
Input circuit of a memory having a lower current dissipation
Input circuit with hysteresis
Input circuit with hysteresis
Input circuit with switched reference signals
Input pad with improved noise immunity and output...
Input receiver with hysteresis
Input/output block with programmable hysteresis
Integrated circuit flip-flops that utilize master and slave...
Integrated circuit for generating a reset signal
Integrated circuit having independently testable input-output ci
Integrated circuit including functional blocks controlled by com
Integrated circuit one shot with extended length output pulse
Integrated circuit operable in a standby mode
Integrated circuit with an active-level configurable and method