Single event upset immune register with fast write access

Details Single event upset immune register with fast write access Single event upset immune register with fast write access

1995-02-21

1996-06-11

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327218, 365156, G11C 1100

Patent

active

055259235

ABSTRACT:
A single event upset hardened bi-stable CMOS circuit has a pair of cross coupled invertors with an isolation resistor in the path coupling the drains of the transistors in each invertor. Each invertor includes a PFET and a NFET pair coupled source to drain. An isolation resistor couples together the drains of each PFET-NFET pair and two low impedance conductive paths provide a direct coupling between the drains of each transistor of one invertor to common gate node of the other invertor.

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H. T. Weaver, et al., "An SEU Tolerant Memory Cell Derived from Fundamental Studies of Mechanisms in SRAM", IEEE 1987.

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