Single event upset hardened latch circuit

Details Single event upset hardened latch circuit Single event upset hardened latch circuit

2000-10-26

2002-07-09

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C326S011000, C326S012000, C365S154000

Reexamination Certificate

active

06417710

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to single event upset (SEU) hardening of latch circuits, and, more particularly to single event upset (SEU) circuits comprised of two cross-coupled inverters.
Circuit designs which provide improved tolerance to SEU are known, see U.S. Pat. No. 4,683,570 to Bedard et al. titled “Self Checking Digital Fault Detector for Modular Redundant Real Time Clock”, issued Jul. 28, 1987; and U.S. Pat. No. 5,031,180 titled “Triple Redundant Fault-Tolerant Register” to McIver et al., issued Jul. 9, 1991. The aforementioned two U.S. patents teach the use of triple redundancy with the outputs connected to three voting circuits which provide feedback to the logic circuit. In Bedard et al., voter circuitry provides an output which is used for failure detection and power-up reset. Bedard et al. being intended for a real time clock. McIver et al. provides SEU hardening for a register by employing triple redundant master slave clocked mux circuitry, each voter circuitry output providing feedback to the output of its slave mux.
BRIEF SUMMARY OF THE INVENTION
In contrast to the preceding prior art, in the present invention the voter output circuitry is fed back to the output mode of the latch circuit instead of the input to the latch. The present single event upset hardened latch circuit, in further contrast includes a voter output circuit which provides increased drive of the output latch circuit. The present latch circuit comprises a novel design hardening approach which is focused at mitigating the effect of SEU at the transistor level rather than the IC output level. This unique design for CMOS or NMOS memory or latch circuits comprises two cross-coupled inverters.


REFERENCES:
patent: 4683570 (1987-07-01), Bedard et al.
patent: 4785200 (1988-11-01), Huntington
patent: 5031180 (1991-07-01), McIver et al.
patent: 5870332 (1999-02-01), Lahey et al.
patent: 7127864 (2000-10-01), Mavis et al.

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