Single-transistor-clocked flip-flop

Details Single-transistor-clocked flip-flop Single-transistor-clocked flip-flop

2005-08-30

2005-08-30

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C326S098000

Reexamination Certificate

active

06937079

ABSTRACT:
The invention provides a low power, high performance flip-flop. The flip-flop uses only one clocked transistor. The single clocked transistor is shared by the first and second branches of the device. A pulse generator produces a clock pulse to trigger the flip-flop. In one preferred embodiment the device can be made as a static explicit pulsed flip-flop which employs only two clocked transistors.

REFERENCES:
patent: 5036217 (1991-07-01), Rollins et al.
patent: 5384493 (1995-01-01), Furuki
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5557225 (1996-09-01), Denham et al.
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5917355 (1999-06-01), Klass
patent: 5990717 (1999-11-01), Partovi et al.
patent: 6064246 (2000-05-01), Endo et al.
patent: 6069495 (2000-05-01), Ciccone et al.
patent: 6097323 (2000-08-01), Koga et al.
patent: 6181180 (2001-01-01), Chen et al.
patent: 6242952 (2001-06-01), Bosshart et al.
patent: 6265923 (2001-07-01), Amir et al.
patent: 6271701 (2001-08-01), DiTommaso
patent: 6424195 (2002-07-01), Samala
patent: 6429711 (2002-08-01), Tschanz et al.
patent: 6433601 (2002-08-01), Ganesan
patent: 6437624 (2002-08-01), Kojima et al.
patent: 6459316 (2002-10-01), Vangal et al.
patent: 2002/0036528 (2002-03-01), Afghahi
patent: 2002/0140481 (2002-10-01), Tschanz et al.
Seongmoo Heo, Ronny Krashinsky, and Krste Asanovie, Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy, 19th Conference on Advanced Research in VLS1, Salt Lake City, UT, Mar. 2001.
Hiroshi Kawaguchi and Takayasu Sakurai, A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998.
Seongmoo Heo and Krste Asanovie, Load-Sensitive Flip-Flop Characterization, IEEE Journal of Solid-State Circuits, 2001.
Bai-Sun Kong, Sam-Soo Kim, and Young-Hyun Jun, Conditional-Capture Flip-Flop for Statistical Power Reduction, IEEE Journal of Solid-State Circuits, vol. 36, No. 8, Aug. 2001.
Jiren Yuan and Christer Svensson, High-Speed CMOS Circuit Technique, IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989.
Rabaey, J.M.: Digital Integrated Circuits, Chapter 7, “Designing Sequential Logic Circuits”, University of California, Berkeley, 2000.
Vladimir Stojanovic and Vojin G. Oklobdzija, Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999.
J. Tschanz, etal., Comparative Delay and Energy of Sgl. Edge-Triggered & Dual Edge-Triggered Pulsed Flip-Flops for Hi-Performance Microprocessors Intn'l Symp. on Low Power Elect and Design, Pp(s): 147-152, 2001.

Affiliated with

Also associated with

Rating

Single-transistor-clocked flip-flop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single-transistor-clocked flip-flop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single-transistor-clocked flip-flop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3522134