Soft-error rate hardened pulsed latch

Details Soft-error rate hardened pulsed latch Soft-error rate hardened pulsed latch

2006-05-02

2006-05-02

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000

Reexamination Certificate

active

07038515

ABSTRACT:
A latch includes a memory unit, a transfer unit, an inversion unit, and an output unit. The Memory unit includes a number of storage nodes. The transfer unit transfers a data from a data input node to the storage nodes via a plurality of data paths. Each of the data paths includes a pass element controlled by a pulse. The inversion unit inverts the data before the data is transferred from the data input node to at least one of the storage nodes. The output unit outputs the data from the memory unit to a latch output node. The memory unit, the transfer unit, the inversion unit, and the output unit of the latch form a soft-error rate hardened latch structure with a reduced number of elements and reduced power consumption.

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Hazucha, Peter, “Measurements and anlysis of SER tolerant latch in a 90nm dual-Vt CMOS process”,Proceedings of the Custom Integrated Circuits Conference, (2003),617-620.

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