Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-11-01
2002-04-30
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000, C327S208000, C326S098000
Reexamination Certificate
active
06380781
ABSTRACT:
FIELD
The present invention relates generally to integrated circuits, and more specifically to integrated circuits having increased soft error rate tolerance.
BACKGROUND
Integrated circuits commonly include components such as latches that retain state information and hold data. During a portion of a time cycle, or clock period, these components hold data to be used during subsequent time cycles. When integrated circuit components reliably retain data, computations can be error free. In contrast, when integrated circuit components do not reliably retain data, computation errors can result.
Cosmic rays and charged particles can cause integrated circuits to be unreliable. When particles bombard portions of integrated circuits, localized areas of charge can build up on an integrated circuit die and cause stored information to be upset. For example, latches having transistors with diffusion regions can be susceptible to bombardment of charged particles. As particles bombard an integrated circuit die about a diffusion region held at a low voltage, the voltage can increase. Likewise, as particles bombard an integrated circuit about a diffusion region held at a high voltage, the voltage can decrease. When the bombardment is significant, the change in voltage in the diffusion region can cause the latch to change state, thereby causing an error to occur.
When an area of an integrated circuit is bombarded with rays or particles, holes and electrons are generated. The generated holes and electrons accumulate charge in localized areas of the integrated circuit. If charge accumulates beyond a device's ability to withstand it, “soft errors” occur. A “soft error” is an error resulting in a change in stored data. For example, a latch within an integrated circuit may be able to withstand a given rate of bombardment without changing the logical state of the latch. When the given rate of bombardment is surpassed, the charge accumulates and causes a soft error.
FIG. 1
shows a prior art latch. Latch
90
includes forward inverter
40
and feedback inverter
10
cross-coupled together. Forward inverter
40
drives feedback node
4
which is input to feedback inverter
10
. Feedback inverter
10
in turn drives storage node
2
which is input to forward inverter
40
.
When latch
90
is holding data, storage node
2
is at a stable logical state of either logical “1” or logical “0,” and buffer
80
drives data output node
85
. Forward inverter
40
receives the stored data value on storage node
2
, and drives feedback node
4
to the opposite logical state than that of storage node
2
. Feedback inverter
10
receives the opposite logical state on feedback node
4
, and drives storage node
2
with the original stored data value.
Transistors within inverters have device sizes associated therewith. For example, within feedback inverter
10
, NFETs
16
and
20
each occupy an area “y” of an integrated circuit die. Likewise, within forward inverter
40
, NFETs
46
and
50
each occupy an area “x” of the integrated circuit die. As used herein, the term NFET describes N channel field effect transistors, of which N channel Metal Oxide Semiconductor (NMOS) FETs are an example, and the term PFET describes P channel field effect transistors, of which P channel Metal Oxide Semiconductor (PMOS) FETs are an example.
Transistors within pass gates also have device sizes associated therewith. For example, in one pass gate, PFET
60
occupies an area “w1,” and NFET
62
occupies an area “w2.” Likewise, in another pass gate, PFET
70
occupies an area “z1,” and NFET
72
occupies an area “z2.” The ratio of area w
1
to area w
2
is typically about 2.5 to 1 because at this ratio, PFETs and NFETs have substantially equal drive strengths. This is also true of the ratio of area z
1
to area z
2
.
FET devices include diffusion regions coupled to the drain of the FET and the source of the FET. Diffusion regions can collect charge resulting from cosmic rays and particles that bombard the integrated circuit die. Particles that bombard the bulk of the integrated circuit die can cause negatively charged electrons or positively charged holes to collect in diffusion regions of FETs and cause soft errors.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for integrated circuit elements tolerant of high soft error rates.
SUMMARY
In one embodiment, an inverter includes an input node, an output node, and a pullup device coupled between a reference node and the output node. The inverter further includes a plurality of pulldown devices coupled in series between the output node and a second reference node, the plurality of pulldown devices occupying unequal areas.
In another embodiment, an inverter having increased soft error rate tolerance includes a PFET having a gate coupled to an input node, and a diffusion region coupled to an output node. The inverter further includes a first NFET having a gate coupled to the input node, a first diffusion region, and a second diffusion region coupled to a second reference node. The inverter additionally includes a second NFET having a gate coupled to a control input, and having a first diffusion region coupled to the output node and a second diffusion region coupled to the first diffusion region of the first NFET, wherein the first diffusion region of the first NFET is a different size than the first diffusion region of the second NFET.
In another embodiment, a latch having increased soft error rate tolerance includes a forward inverter having an input coupled to a storage node and an output coupled to a feedback node, and a feedback inverter having an input coupled to the feedback node and an output coupled to the storage node. In this embodiment, the feedback inverter includes a first pulldown device coupled to a first reference node, the first pulldown device having a control input coupled to the input of the feedback inverter, and a second pulldown device coupled between the first pulldown device and the output of the feedback inverter, the second pulldown device having a control input coupled to a latch load node of the latch. Also in this embodiment, a feedback node capacitance resulting from the control input of the first pulldown device is greater than a latch load node capacitance resulting from the control input of the second pulldown device.
REFERENCES:
patent: 5498989 (1996-03-01), Diba
patent: 5552738 (1996-09-01), Ko
patent: 6104234 (2000-08-01), Shin et al.
Borkar Shekhar Y.
Karnik Tanay
Soumyanath Krishnamurthy
Callahan Timothy P.
Nguyen Minh
Schwegman Lundberg Woessner & Kluth P.A.
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