Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-11-24
2002-04-09
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C365S154000, C365S156000, C327S208000
Reexamination Certificate
active
06369630
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates to a single-event upset (SEU) hardened integrated circuit, and, more particularly to an SEU hardened asymmetric bi-stable CMOS latch wherein when the latch is powered-up it is set to a predetermined state.
BACKGROUND OF THE INVENTION
In combinational logic circuits, data latches are susceptible to single-event upsets (SEUs). The radiation hardness requirements imposed on systems used in space and strategic applications necessitate that the data latches in logic chips be SEU hardened. Data latches are used in latch chains and as separate logic gates for data manipulation in storage. Several data latches may lie in critical signal paths, so consequently, data latch hardening techniques must preserve latch speed. Data latches outside the critical signal paths do not require as high performance level as data latches which are located in a critical signal path. The hardness against SEUs (i.e., ability to withstand single particle hits without logic upset) may be achieved by virtue of the design of the data latch or through the fabrication process or a combination of both. Design hardening offers the most practical approach to gaining SEU protection without seriously degrading latch performance.
Programmable logic circuits (e.g., field programmable gate arrays (FPGAs)) are used widely in digital system designs. Programmable logic circuits are comprised of an array of unconnected logic elements that can be programmed (i.e., configured) to form a complex logic circuit to accomplish a prescribed function. Most programmable logic circuits employ fuses, anti-fuses, or custom designed metal mask levels to configure the logic elements. Once configured, the resulting logic circuit design is permanent (“firm”) and cannot be altered later.
Reconfigurable (or “reprogrammable”) logic circuits can be changed to form a different logic function on demand. Reconfigurable logic circuits generally employ a bi-stable data storage clement (e.g., a data latch or an SRAM cell) within which the logic configuration data is stored. Depending on whether a logical “one” or logical “zero” data is stored in the data storage element, the logic, configuration interface gate or device connected to the data storage element's output is either on or off. In that way, blocks of previously unconnected logic elements are connected and the logic circuit is configured. Selectively changing the data stored in some of the data storage elements allows one to reconfigure the logic circuits when desired. Reconfigurable logic circuits offer a significant advantage over one-time programmable “firm” logic circuits in that the hardware can be changed even after the digital system has been deployed for many years.
There is a lot of reluctance to use reconfigurable logic circuits in space and military applications that generally must operate in stringent, noisy radiation environments. The major fear is that the logic-configuration data storage elements may be strick by a single-event upset (SEU) inducing heavy ion, upsetting the data stored, and thereby unintentionally reconfigure the logic circuit. Ways to circumvent this threat involve techniques like triple module redundancy, for example, which requires significant amounts of design and operation overhead and are never completely fool proof.
As used herein and as known in the art, complimentary MOS (CMOS) refers to integrated circuits which employ both p-channel field effect transistor devices (PFET) and n-channel field effect transistor devices (NFET) which are connected so as to provide high speed, low power dissipation, integrated circuits for logic and memory applications. The abbreviation NFET is used herein to refer to an enhancement mode n-channel field effect transistor device. Such devices are generally fabricated by forming an N-type conductivity source diffusion and N-type drain diffusion in the surface of a P-type conductivity silicon substrate. The channel region of the substrate separating the source and drain regions, is covered by a gate insulator layer and a gate electrode. An enhancement mode NFET is normally non-conducting between its source and drain and it can be switched into conduction by applying a positive potential to its gate electrode, with respect to the potential of its source.
The abbreviation PFET will be used herein to refer to an enhancement mode p-channel field effect transistor device. Such devices are generally fabricated by forming P-type conductivity source diffusion and P-type conductivity drain diffusions within an N-type conductivity diffusion called an N-well which, in turn, has been formed in the P-type semiconductor substrate for the integrated circuit. The channel region of the N-well separating the P-type source and drain diffusions is covered by the gate insulator layer and the gate electrode. An enhancement mode PFET is normally non-conducting between a source and drain when the gate-to-source potential is relatively negative, the opposite condition from that obtaining from an NFET device relative to biasing.
In steady state operation, when the gate inputs are low (approximately 0 volts) the n-channel devices are turned off (non-conducting) and the p-channel devices are turned on (conducting). When the gate inputs are high (VDD) the n-channel devices are turned on and the p-channel devices are turned off.
SUMMARY OF THE INVENTION
In one embodiment, the present invention provides a single event upset (SEU) hardened integrated circuit. The integrated circuit includes an asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, where upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state.
In one aspect, the asymmetric CMOS bi-stable latch includes a first CMOS inverter and a second CMOS inverter. The second CMOS inverter is cross-coupled to the first CMOS inverter, wherein the first CMOS inverter is asymmetric with the second CMOS inverter. The first CMOS inverter includes a first data node having a first nodal capacitance, and the second CMOS inverter includes a second data node having a second nodal capacitance different from the first nodal capacitance which defines the asymmetry between the first CMOS inverter and the second CMOS inverter.
The first CMOS inverter includes a first p-channel transistor and a first n-channel transistor. The second CMOS inverter includes a second p-channel transistor and a second n-channel transistor. The drain area of the first n-channel transistor is greater than the drain area of the second n-channel transistor. In one aspect, the drain area of the first n-channel transistor is more the four times the drain area of the second n-channel transistor.
In one embodiment, the SEU hardened asymmetric bi-stable CMOS latch includes an SEU hardening component. In one aspect, the SEU hardening component is a thin film resistor. In one aspect, the asymmetric bi-stable CMOS latch includes a first CMOS inverter and a second CMOS inverter. The second CMOS inverter is cross-coupled to the first CMOS inverter via a first coupling segment and a second coupling segment. The first CMOS inverter is asymmetric with the second CMOS inverter. The SEU hardening component is a thin film resistor positioned in the first coupling segment. Optionally, the SEU hardening component may be positioned in the first coupling segment, the second coupling segment, or both the first coupling segment and second coupling segment. Preferably, the thin film resistor is a polysilicon resistor.
The asymmetric bi-stable CMOS latch is reconfigurable between the first logic state and the second logic state, and may further include a switch for switching the asymmetric bi-stable CMOS latch between the first logic state and the second logic state. In one aspect, the switch includes an n-channel transistor. The latch further includes a pulsed input signal received by the n-channel transistor for switching the asymmetric bi-stable CMOS la
BAE Systems Information and Electronic Systems Integration Inc.
Dicke, Billing & Czaja, P.A.
Lam Tuan T.
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