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TAP with enable input gated and multiplexed mode select

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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TAP with select output from one of IR and DR

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Tap with separate scan cell in series with instruction register

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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TAP, ST, lockout, and IR SO enable output data control

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Tap-selectable reduced state sequence estimator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Tapping a memory card

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Target control abstraction for debugging embedded systems

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Target debugging application on digital signal processor...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Target device-specific syntax and semantic analysis for a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Target value search circuit, taget value search method, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Targeted data protection

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Targeted fault tolerance by special CPU instructions

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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TCAM BIST with redundancy

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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TCAM BIST with redundancy

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Technical support chain automation with guided self-help...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technical support for software products

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for automatically generating a software test plan

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for combining scan test and memory built-in self test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Technique for combining scan test and memory built-in self test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Technique for correcting errors in position encoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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