Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2010-08-03
2011-10-11
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000
Reexamination Certificate
active
08037386
ABSTRACT:
A TAP linking module (21, 51) permits plural TAPs (TAPs1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).
REFERENCES:
patent: 4315313 (1982-02-01), Armstrong et al.
patent: 5056093 (1991-10-01), Whetsel
patent: 6539497 (2003-03-01), Swoboda et al.
Ruparel, K.N.; Chin, C.; Fitzgerald, J.;, “A vertically integrated test methodology based on JTAG IEEE 1149.1 Standard Interface,” ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International, vol., No., pp. P11-4/1-4, Sep. 23-27, 1991 doi: 10.1109/ASLC.1991.242912.
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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