Targeted fault tolerance by special CPU instructions

Details Targeted fault tolerance by special CPU instructions Targeted fault tolerance by special CPU instructions

2006-12-05

2006-12-05

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S013000

Reexamination Certificate

active

07146530

ABSTRACT:
One embodiment disclosed relates to a microprocessor for targeted fault-tolerant computing. The microprocessor's decode circuitry is configured to decode a fault-tolerant version of an instruction and a non-fault-tolerant version of the instruction distinctly from each other. The microprocessor's execution circuitry is configured to execute the fault-tolerant version of the instruction with redundancy checking and to execute the non-fault-tolerant version of the instruction without redundancy checking.

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Joydeep Ray, et al. “Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery”, International Symposium on Microarchitecture archive, 2001, pp. 214-224, IEEE Computer Society, Washington, DC, USA.

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