Technique for combining scan test and memory built-in self test

Details Technique for combining scan test and memory built-in self test Technique for combining scan test and memory built-in self test

2008-03-04

2008-03-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C365S201000

Reexamination Certificate

active

11008877

ABSTRACT:
Semiconductor devices including logic circuitry and embedded memories may be tested using one or more flip-flops in a scan chain that are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.

REFERENCES:
patent: 5568437 (1996-10-01), Jamal
patent: 5761215 (1998-06-01), McCarthy et al.
patent: 6415403 (2002-07-01), Huang et al.
patent: 6560740 (2003-05-01), Zuraski et al.
patent: 6681359 (2004-01-01), Au et al.
patent: 2002/0138802 (2002-09-01), Firth et al.
patent: 2004/0083412 (2004-04-01), Corbin et al.
patent: 2004/0098643 (2004-05-01), Schulz
patent: 2004/0190331 (2004-09-01), Ross et al.
patent: 2005/0120284 (2005-06-01), Ouellette et al.
patent: 0 747 941 (1996-12-01), None
patent: 1 122 771 (2001-08-01), None
patent: 06102327 (1992-09-01), None
“A scan-BIST environment for testing embedded memories” Karimi et al. 2002 IEEE International Workshop on Memory Technology, Design and Testing, 2002 Proceedings Publication Date: 2002 On pp. 17-23 ISSN: 1087-4852 ISBN: 0-7695-1617-3 INSPEC Accession No. 7425855.
“A scan-BIST environment for testing embedded memories” by Karimi et al. This paper appears in: On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International Publication Date: 2002 On pp. 211-217 ISBN: 0-7695-1641-6 INSPEC Accession No. 7425843.
“Designing built-in self-test circuits for embedded memories test” by Park et al. This paper appears in: ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on Publication Date: 2000 On pp. 315-318 ISBN: 0-7803-6470-8 INSPEC Acession No. 6866824.

Affiliated with

Also associated with

Rating

Technique for combining scan test and memory built-in self test does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Technique for combining scan test and memory built-in self test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for combining scan test and memory built-in self test will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3936012