Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-03
2011-05-03
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
07937637
ABSTRACT:
A TAP Linking Module (TLM) couples plural TAPs, via select and enable signals, to an externally accessible IEEE 1149.1 interface. The select signals are outputs from the TAPs to the TLM, and the enable signals are output from the TLM to the TAPs. Each select signal is output in response to a special instruction scanned into a TAP's instruction register, which causes the TLM to be selected as the data register scan path between the TDI and TDO pins. A conventional data register scan operation shifts data through the TLM. Following the scan operation, the TLM outputs one enable signal to the TAPS and outputs select signals to a multiplexer to establish a TAP link configuration.
REFERENCES:
patent: 4894830 (1990-01-01), Kawai
patent: 5054024 (1991-10-01), Whetsel
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5341380 (1994-08-01), Shoda
patent: 5570375 (1996-10-01), Tsai et al.
“IEEE Standard Test Access Port and Boundary—Scan Architecture,” IEEE Std 1149.1-1990 , vol., No., pp. 0—1, 1990 doi: 10.1109/IEEESTD.1990.114395.
Bassuk Lawrence J.
Brady W. James
Britt Cynthia
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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