Technique for combining scan test and memory built-in self test

Details Technique for combining scan test and memory built-in self test Technique for combining scan test and memory built-in self test

2008-03-04

2008-03-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C365S201000

Reexamination Certificate

active

07340658

ABSTRACT:
Semiconductor devices including logic circuitry and embedded memories may be tested using one or more flip-flops in a scan chain that are connected to a control input of an MBIST logic, thereby allowing the control of the MBIST logic during a simultaneous scan test and memory test run. By combining the output of the MBIST logic with the output of the scan chain, fault diagnosis is maintained.

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