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Selected: M

Memory with embedded error correction codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory with fault tolerant reference circuitry

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Memory with integrated programmable controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory with integrated programmable controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory with test mode output

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory wrap test mode using functional read/write buffers

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Memory-based shuffle-exchange traceback for gigabit Ethernet...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory-based shuffle-exchange traceback for gigabit ethernet...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory-based trigger generation scheme in an emulation...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Memory-embedded LSI

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory-minimized architecture for implementing map decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory-module burn-in system with removable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Memory-module controller, memory controller and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Memory-mounting integrated circuit and test method thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Memory/Transmission medium failure handling controller and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Merged data line test circuit for classifying and testing a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Merged memory and logic (MML) integrated circuits including buil

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Merged memory and logic (MML) integrated circuits including...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Merged MISR and output register without performance impact...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Merging cluster nodes during a restore

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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