Memory-module controller, memory controller and...

Details Memory-module controller, memory controller and... Memory-module controller, memory controller and...

2007-04-26

2011-12-13

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

08078937

ABSTRACT:
A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

REFERENCES:
patent: 6308244 (2001-10-01), Katayama
patent: 6941505 (2005-09-01), Yada et al.
patent: 7076618 (2006-07-01), Dahlen et al.
patent: 7114117 (2006-09-01), Tamura et al.
patent: 4406258 (2008-07-01), None
patent: 1703400 (2006-09-01), None
patent: 2005/066965 (2005-07-01), None

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