Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-04-14
2001-04-10
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S189020, C365S201000
Reexamination Certificate
active
06216240
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices, and more particularly to testing of integrated circuit devices.
BACKGROUND OF THE INVENTION
Integrated circuit devices, such as integrated circuit memory devices and integrated circuit logic devices, are widely used in consumer and commercial applications.
Recently, merged memory and logic (MML) integrated circuits have been developed. MML integrated circuits generally include a large capacity memory and a large logic block that are merged in one integrated circuit. The large capacity memory is generally divided into a plurality of memory blocks, also referred to as “memories”. The logic block may also be referred to as a “logic circuit” or simply as a “logic”. Thus, an MML integrated circuit can replace discrete memory and logic chips that are used in personal computers and other consumer and commercial devices.
MML integrated circuits present new challenges for the testing thereof. In particular, the MML integrated circuit generally provides a large number of internal data pads between the memory block and the logic block. For example, up to 256 or more internal pads may be provided. Since many of these internal pads are not brought out to external MML integrated circuit pads, it may be difficult to access all of the internal data pads in order to test the memory block.
Stated differently, in order to test a conventional memory integrated circuit, test equipment is connected to the pads of the memory integrated circuit. However, the memory block in an MML integrated circuit may be difficult to test because the memory is connected to the external pads through the logic block. Accordingly, additional pads may be needed to test the memory of the MML integrated circuit. Unfortunately, the addition of large numbers of test pads may increase the cost, size and/or complexity of the MML integrated circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved testing circuits and methods for MML integrated circuits.
It is another object of the present invention to provide testing methods and circuits for MML integrated circuits that can reduce the number of additional pads that are used for memory testing.
These and other objects are provided, according to the present invention, by providing a memory test control circuit in an MML integrated circuit. The memory test control circuit is connected to a first pad which receives memory control signals to control first and second memories of the MML circuit. The memory test control circuit is also connected to a second pad which receives memory data signals for the first and second memories. The memory test control circuit is also connected to the logic block and to the first and second memories. The memory test control circuit transmits the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and transmits the memory control signals and the memory data signals to the logic block during normal operation of the MML integrated circuit. Accordingly, the memory test control circuit allows pass-through of memory data and control signals directly to the memory blocks during test mode, and provides the memory data and control signals to the logic block during normal operations.
In a preferred embodiment of the present invention, the memory test control circuit includes means for generating a first control signal to indicate a test of a first one of the memory blocks, for generating a second control signal to indicate a test of the second one of the plurality of memory blocks, and for generating a third control signal to indicate the normal operation mode for the MML integrated circuit, in response to the test control signal. First means for controlling the first and second memory blocks and the logic block is provided. The first means transmits the memory control signals from the first pad to the first memory block in response to the first control signal, transmits the memory control signals from the first pad to the second memory block in response to the second control signal and transmits the memory control signals from the first pad to the logic block in response to the third control signal. Second means for controlling the first and second memory blocks and the logic block is also provided. The second means transmits the memory data signals from the second pad to the first memory block in response to the first control signal, transmits the memory data signals from the second pad to the second memory block in response to the second control signal and transmits the memory data signals from the second pad to the logic block in response to the third control signal. Analogous methods of operating MML integrated circuits are also provided.
The memory test control circuit may include a memory control signal controller that transmits the memory control signals from the first pads to the first and second memories and to the logic block. The memory data controller transmits the memory data signals from the second pad to the first and second memories and transmits memory data signals generated from the first and second memories and the logic block to the second pad. A main control signal generator is connected to the memory control signal controller and to the memory data controller. The main control signal generator generates main control signals to control transmission of the memory control signals to the first and second memories and to the logic block in response to a test control signal, to control transmission of the memory data signals to the first and second memories and the logic block and to control transmission of the memory data signals generated from the first and second memories and the logic block to the second pad. Preferred embodiments of the memory control signal controller, the memory data controller and the main control signal generator are also provided. Accordingly, testing of memory blocks in an MML integrated circuit may be accomplished without the need to add large numbers of pads to the MML integrated circuit for internal access to the memory blocks.
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Park Sang-bong
Won Jong-Hak
De'cady Albert
Lamarre Guy
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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