Merged memory and logic (MML) integrated circuits including buil

Details Merged memory and logic (MML) integrated circuits including buil Merged memory and logic (MML) integrated circuits including buil

1998-04-14

2000-12-05

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714718, 36518902, 365201, G01R 3128, G11C 2900

Patent

active

061580368

ABSTRACT:
MML integrated circuits include a memory block and a logic block that is connected to the memory block. A test enable pad and a test results pad are also provided. The MML integrated circuit also includes a built-in self-tester that is responsive to a test enable signal on the test enable pad, to test the memory block and to provide the test results on the test results pad. A clock pad may also be provided wherein the built-in self-tester is responsive to the test enable signal on the test enable pad and to a clock signal on the clock pad. The built-in self-tester preferably tests the memory block by providing control signals to the memory block and obtaining data that is read from the memory block.

REFERENCES:
patent: 5535164 (1996-07-01), Adams et al.
patent: 5568437 (1996-10-01), Jamal
patent: 5764655 (1998-06-01), Kirihata et al.
patent: 5825783 (1998-10-01), Momohara
patent: 5848016 (1998-12-01), Kwak
patent: 5926420 (1999-07-01), Kim
patent: 5969999 (1999-10-01), Lee

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