Memory wrap test mode using functional read/write buffers

Details Memory wrap test mode using functional read/write buffers Memory wrap test mode using functional read/write buffers

2006-08-22

2009-08-04

McCarthy, Christopher S (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S768000, C714S030000, C714S763000

Reexamination Certificate

active

07571357

ABSTRACT:
A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.

REFERENCES:
patent: 2001/0052090 (2001-12-01), Mio
patent: 2007/0133399 (2007-06-01), Gangwal
patent: 2007/0234182 (2007-10-01), Wickeraad et al.

Affiliated with

Also associated with

Rating

Memory wrap test mode using functional read/write buffers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory wrap test mode using functional read/write buffers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory wrap test mode using functional read/write buffers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4081032