Memory with fault tolerant reference circuitry

Details Memory with fault tolerant reference circuitry Memory with fault tolerant reference circuitry

2004-07-15

2008-10-28

Perveen, Rehana (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000

Reexamination Certificate

active

07444557

ABSTRACT:
A memory not only uses redundant cells but also redundant references to reduce the likelihood of a failure. In one approach a failure in a reference can cause both the primary cell as well as the redundant cell to be ineffective. To overcome this potential problem two references for each bit are employed. In one form, the primary cell of a first bit is compared to one reference and the redundant cell of the first bit is compared to another reference. The primary and redundant cell of a second bit can use these two references as well. In another aspect, two references are placed in parallel for both the primary and redundant cell of the bit.

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