Memory with embedded error correction codes

Details Memory with embedded error correction codes Memory with embedded error correction codes

2005-09-08

2009-08-25

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714SE11056

Reexamination Certificate

active

07581153

ABSTRACT:
A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

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Tanzawa, T., et al., “A Compact On-Chip ECC For Low-Cost Flash Memories,”IEEE J. Solid-State Circuits, 32(5):662-669, May 1997.

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