Architecture and control of reed-solomon error-correction...

Architecture and control of reed-solomon list decoding

Architecture and logic to control a device without a JTAG...

Architecture and method for testing of an integrated circuit...

Architecture for a message bus

Architecture for an iterative decoder

Architecture for built-in self-test of parallel optical...

Architecture for handling errors in accordance with a risk...

Architecture for handling errors in accordance with a risk...

Architecture for high availability using system management...

Architecture for managing disk drives

Architecture for managing failover and recovery after...

Architecture for managing failover and recovery after...

Architecture for soft decision decoding of linear block...

Architecture of an efficient at-speed programmable memory...

Architecture, circuitry and method for controlling a...

Architecture, circuitry and method for testing one or more...

Area efficient BIST system for memories

Area efficient memory architecture with decoder self test...

Area efficient parallel turbo decoding