Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-07-12
2005-07-12
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S820000, C714S724000
Reexamination Certificate
active
06918057
ABSTRACT:
Architecture, circuitry, and methods are provided for programming, writing to, or reading from one or more integrated circuits which may be arranged upon a printed circuit board. Programming and read/write operations can, therefore, be done after integrated circuits are populated upon a printed circuit board to control those integrated circuits using a standard JTAG interface, well-known as the IEEE Std. 1149.1 interface. A shift register used to control one or more electronic subcomponents can be programmed, written to, or read from using JTAG programming languages. However, the shift register, or multiple shift registers, used to control electronic subcomponents need not be JTAG compliant. The shift registers may be those found within proprietary circuits, such as analog-to-digital converters or digital-to-analog converters, and include any shift register than receives serial data and produces parallel data, or vice-versa, where the loading and serial shifting of data is controlled using a generic interface, such as enable, reset, capture, etc. One or more shift registers can be distributed among one or more integrated circuits proprietary to the manufacturer of that circuit, and the circuits which embody the shift registers need not have a JTAG interface. Yet, the shift registers can be controlled by a single test access port (TAP) external to the integrated circuits, but which controls the non-JTAG compliant shift registers of each integrated circuit bearing the same. This allows a JTAG programming language which can be readily obtained off-the-shelf to control integrated circuits which do not recognize JTAG control signals, nor do such integrated circuits necessarily have a JTAG four-pin interface.
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Brophy Brenor L.
Nadavi Dinesh
Xi Xiao Ming
Beausoliel Robert
Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Duncan Marc
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