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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically replacing a failed chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Dynamically-tunable memory controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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