Dynamically replacing a failed chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

active

06567950

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to computer systems having a DRAM memory and, more particularly, to computer systems having DRAM memories, wherein failed chips or chip sets or chip I/O can be replaced with good chips or chip sets OR I/O without having to replace the entire memory or reboot.
BACKGROUND INFORMATION
The amount of memory on a DIMM or SIMM card utilized in a computer system increases, and the number of chips which constitute or make-up the memory card also increases. With the increasing number of DRAM chips on a DIMM or SIMM card, there is an increased potential or possibility of failure of one or more of these chips. In order to obviate the need for discarding an entire memory card if a single chip fails, there have been proposals for so called “Chip Sparing” in which one or more “spare” chips are provided on the SIMM or DIMM card, i.e. a chip that is not normally used for data storage. When a chip fails, this “spare” chip is then inserted into the system in place of the failed chip, sometimes referred to as chip kill, and the memory is allowed to continue. In the past, this chip replacement has been accomplished by completely shutting the system down and replacing the memory system with the spare chip switched into the memory system in place of the failed chip, which insertion has been done with the system powered down and the system then rebooted; or, in the alternative, with some more sophisticated systems, the memory card is switched off-line and reinitialized with the spare chip. The rebooting of the system or re-initialization of the memory card is time consuming and disruptive of continuous operation of a computer system.
SUMMARY OF THE INVENTION
According to the present invention, an improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or spare chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.


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NN73033052(Dynamic Configuration; IBM Technical Disclosure Bulletin, Mar. 1973, US, vol. No.: 15, p. No.: 3052-3055).*
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“Memory Error Correction Technique”, IBM Technical Disclosure Bulletin, vol. 28, No. 2, Jul., 1985.

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