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Structural input levels testing using on-die levels generators

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Structure and method for depuncturing punctured codes for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Structure and method for detecting errors in a multilevel...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Structure and method for verifying data in a non-JTAG device...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Structure and method of repairing SDRAM by generating...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Structure and method with which to generate data background...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Structure for redundancy programming of a memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Structure for system for and method of performing high speed...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Structured data communication with backwards compatibility

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Structured interleaving/de-interleaving scheme for product...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Structured low-density parity-check (LDPC) code

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Stuck-at fault scan chain diagnostic method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Stumping mechanism

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Sub-packet adaptation in a wireless communication system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Subframe interleaving

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Super high speed viterbi decoder using circularly connected...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Supervoltage detection circuit having a multi-level reference vo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Supporting cyclic redundancy checking for PCI-X

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Surveillance of quality of service in a digital television link

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Survival selection rule

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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