Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-01-11
2011-01-11
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S719000
Reexamination Certificate
active
07870454
ABSTRACT:
A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
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U.S. Appl. No. 11/531,035, filed Sep. 12, 2006, entitled System for and Method of Performing High Speed Memory Diagnostics via Built-In-Self-Test, Inventors: Kevin W. Gorman, Emory D. Keller, Michael R. Ouellette and Donald L. Wheater.
Notice of Allowance dated Jun. 4, 2009, with regard to related U.S. Appl. No. 11/531,035.
Gorman Kevin W.
Keller Emory D.
Ouellette Michael R.
Wheater Donald L.
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Kerveros James C
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