Structured interleaving/de-interleaving scheme for product...

Details Structured interleaving/de-interleaving scheme for product... Structured interleaving/de-interleaving scheme for product...

2005-06-27

2008-10-07

Torres, Joseph D (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S756000, C714S804000

Reexamination Certificate

active

07434138

ABSTRACT:
A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). In one embodiment, an encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. A corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

REFERENCES:
patent: 4547882 (1985-10-01), Tanner
patent: 5299208 (1994-03-01), Blaum et al.
patent: 5465260 (1995-11-01), Zook
patent: 5751730 (1998-05-01), Mourot
patent: 5991857 (1999-11-01), Koetje et al.
patent: 6681362 (2004-01-01), Abbott et al.
patent: 7093179 (2006-08-01), Shea

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