Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-05-16
2006-05-16
Torres, Joseph (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
07047467
ABSTRACT:
According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.
REFERENCES:
patent: 5048021 (1991-09-01), Jarwala et al.
patent: 5497378 (1996-03-01), Amini et al.
patent: 5706297 (1998-01-01), Jeppesen et al.
patent: 5708773 (1998-01-01), Jeppesen et al.
patent: 6757844 (2004-06-01), Lulla et al.
XAPP017 (v3.0), “Boundary-scan in XC4000, Spartan and XC5200 Series Devices”, available from Xilinx, Inc., 2100 Logic Drive, San Jose CA 95124, Nov. 16, 1999, pp 1-17.
Khu Arthur H.
Shokouhi Farshid
Theron Conrad A.
Liu Justin
Maunu LeRoy D.
Torres Joseph
Xilinx , Inc.
Young Edel M.
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