Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-03-07
2006-03-07
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S799000
Reexamination Certificate
active
07010735
ABSTRACT:
While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying operating parameters, such as power supply and reference voltages, clock timing patterns, temperature and timing sequences, one or more latches down the SRL chain from the stuck-at fault location may be triggered to change state from the stuck-at fault value. The SRL chain is then operated to shift data out the output of the SRL chain. The output is monitored and any change in value from the stuck-at state is noted as identifying all good latch positions to end of the chain. The process is repeated: varying each of the selected operating parameters until the latch position following the stuck-at fault latch is identified.
REFERENCES:
patent: 5303246 (1994-04-01), Anderson et al.
“A Technique for Fault Diagnosis of Defects in Scan Chains”, Guo et al., Int'l Test Conference Proceedings 2001, Oct. 30-Nov. 1, 2001, pp 268-277.
“Fast Technique for Locating Faults in Shift Register Latches”, IBM Technical Bulletin NN7906229, Jun., 1979.
“Combined Multi Corner Testing with Time and or Voltage Modulation”, IBM Technical Bulletin NN81081677, Aug. 1981.
“Measurement of Power Bus Noise Sensitivity of VLSI Circuits with Automated Functional Tester”, IBM Technical Disclosure NN9201226.
Motika Franco
Nigh Philip J.
Song Peilin
Augspurger Lynn L.
De'cady Albert
Murray James E.
Trimmings John P.
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