Dynamically reconfigurable precision signal delay test...
Dynamically reconfigurable precision signal delay test...
Dynamically reconfigurable shared scan-in test architecture
Dynamically reconfigurable shared scan-in test architecture
Dynamically reconfigurable shared scan-in test architecture
Dynamically reconfigurable shared scan-in test architecture
Dynamically reconfigurable shared scan-in test architecture
Dynamically replacing a failed chip
Dynamically-tunable memory controller