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Techniques for reducing clock skew in clock routing networks

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Reexamination Certificate

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Techniques for reducing leakage current in on-chip impedance...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Techniques for reducing leakage current in on-chip impedance...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Techniques for reducing power requirements of an integrated...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

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Techniques for serially transmitting on-chip termination...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Techniques for serially transmitting on-chip termination...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Techniques for trimming drive current in output drivers

Electronic digital logic circuitry – Interface – Current driving

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Techniques for trimming drive current in output drivers

Electronic digital logic circuitry – Interface – Current driving

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Technology for supressing noise of data bus circuit

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Temperature adaptive refresh clock generator for refresh...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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Temperature and supply insensitive TTL or CMOS to 0/-5 V transla

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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Temperature variance nullification in an inrush current...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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Temperature variance nullification in an inrush current...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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Temperature-compensated output buffer method and circuit

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

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Temperature-independent, linear on-chip termination resistance

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Temperature-insensitive current controlled CMOS output driver

Electronic digital logic circuitry – Tri-state – With field-effect transistor

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Terminating circuit for a transmission line

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Terminating resistance adjusting method, semiconductor...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Terminating resistor device and a method for testing a...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Terminating resistor driver for high speed data communication

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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