Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-06-24
2008-06-24
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S086000, C327S108000
Reexamination Certificate
active
07391229
ABSTRACT:
Techniques are provided for controlling on-chip termination (OCT) impedance using OCT calibration blocks that serially transmit OCT control signals to input/output (IO) blocks. The OCT control signals are serially transmitted through a shared conductor. An OCT calibration block can transmit OCT control signals to one or multiple IO blocks. The IO blocks can be programmed to select OCT control signals from one of the calibration blocks. Enable signals enable one or more of the IO blocks to receive the selected OCT control signals. The OCT control signals are used to control the on-chip termination impedance at one or more IO buffers.
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“Virtex-II Pro and Virtex-II Pro X FPGA User Guide,” Mar. 23, 2005, pp. 223-240.
Doan Quyen
Santurkar Vikram
Yi Hyun Mo
Altera Corporation
Barnie Rexford
Cahill Steven J.
Lo Christopher
LandOfFree
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