Technology for supressing noise of data bus circuit

Details Technology for supressing noise of data bus circuit Technology for supressing noise of data bus circuit

2005-04-29

2008-08-12

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S021000

Reexamination Certificate

active

07411416

ABSTRACT:
A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a data bus that electrically connects the south bridge and the bay, and a Thevenin termination circuit that is arranged on the data bus at a point. The Thevenin termination circuit maintains a voltage at the point substantially equal to the first voltage.

REFERENCES:
patent: 5406118 (1995-04-01), Saito
patent: 5841995 (1998-11-01), Ogawa
patent: 2005/0253622 (2005-11-01), Dreps et al.
patent: 3-235111 (1991-10-01), None
Agilent Technologies□□Title: Agilent HDMP-1032A/1034A Transmitter/Receiver Chip Set Data Sheet□□Date: Aug. 16, 2001□□Pertinent pp. 1-31 (Examiner cited pp. 4, 12, and 28).
Agilent Technologies□□Agilent HDMP-1032A/1034A Transmitter/Receiver Chip Set Data Sheet□□Pertinent Pages (all pages of Data Sheet)□□Date Aug. 16, 2001.
Agilent Technologies, Inc., Agilent HDMP-1032A/1034A Transmitter/Receiver Chip Set Data Sheet, Aug. 16, 2001, pp. 1-31.

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