Temperature and supply insensitive TTL or CMOS to 0/-5 V transla

Details Temperature and supply insensitive TTL or CMOS to 0/-5 V transla Temperature and supply insensitive TTL or CMOS to 0/-5 V transla

1994-04-06

1995-05-30

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 68, 326116, 327378, H03K 190175

Patent

active

054205271

ABSTRACT:
Voltage translator apparatus to translate TTL or CMOS logic level inputs to 0/-5 V logic levels that is insensitive to temperative and bias supply variation. A unique circuit structure comprises a level shift stage employing transistors configured to level shift a source of operating potential to a controlling potential to be applied to a predriver stage. The controlling potential is a function of the input logic levels. The predriver stage drives an output stage capable of providing complementary 0/-5 V logic outputs. The configuration is such as to afford low power consumption as well as proper operation over wide bias supply and temperature ranges.

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patent: 5128556 (1992-07-01), Hirakata
patent: 5323071 (1994-06-01), Hirayama

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