Temperature-independent, linear on-chip termination resistance

Details Temperature-independent, linear on-chip termination resistance Temperature-independent, linear on-chip termination resistance

2005-12-15

2009-02-24

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S032000, C326S026000, C326S027000, C326S029000

Reexamination Certificate

active

07495467

ABSTRACT:
In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.

REFERENCES:
patent: 5382841 (1995-01-01), Feldbaumer
patent: 5953811 (1999-09-01), Mazzochette
patent: 6147481 (2000-11-01), Mazzochette et al.
patent: 6924659 (2005-08-01), Andrews et al.
patent: 2004/0189343 (2004-09-01), Jang
patent: 2006/0166457 (2006-07-01), Liu et al.

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