Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2000-10-24
2001-12-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S083000
Reexamination Certificate
active
06326803
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a terminating circuit, and specifically, relates to a terminating circuit that prevents reflection at the termination of a transmission circuit when a signal is transmitted by using a transmission line.
BACKGROUND OF THE INVENTION
Generally, when conducting the transmission and reception of a digital signal through the medium of a transmission line, if the impedance of the transmission line does not match the input impedance of the receiver side, a signal is reflected at the termination of the transmission line, and waveform distortion is created. Thus, a resistor having a resistance value equal to the impedance of the transmission line is connected between the termination of the transmission line and ground potential. By this means, reflection at the termination of the transmission line is prevented, and the transmission and reception of a digital signal without any waveform distortion becomes possible.
However, in the case of connecting a resistor between the transmission line termination and ground potential, when a signal of a high level is output on the transmission line, a current flows to the ground through the medium of the resistor, and there is a problem that the power consumption loss is great.
As a countermeasure for this, instead of a resistor, a terminating circuit using a MOSFET in place of the resistor has been proposed.
Key
101
in
FIG. 10
shows one example of a conventional digital transmission line. This digital transmission line has a driver
102
, a receiver
103
, and a transmission line
104
, and is constructed so that a signal voltage that is output from the driver
102
is received at the receiver
103
through the medium of the transmission line
104
.
A terminating circuit
111
is provided in this transmission circuit
101
. The terminating circuit
111
has CMOS inverters
116
,
117
.
The CMOS inverter
116
is made of a p-channel MOS transistor
114
and an n-channel MOS transistor
115
, its input terminal is connected to a termination
105
of the transmission line, and a signal corresponding to the level of the signal voltage of the termination
105
of the transmission line is output from the output terminal.
The CMOS inverter
117
is made of a p-channel MOS transistor
112
and an n-channel MOS transistor
113
, [these] are respectively arranged with the p-channel MOS transistor
112
[connected to] the power supply voltage Vcc side and the n-channel MOS transistor
113
connected to the ground side, and the output terminal is connected to the transmission line termination
105
, and when the output signal of the CMOS inverter
116
is at a high level, the transmission line termination
105
is connected to the ground terminal through the medium of the n-channel MOS transistor
113
, and when the output signal is at a low level, the transmission line termination
105
is connected to the power supply voltage Vcc through the medium of the p-channel MOS transistor
112
.
In the above-mentioned circuit
101
, when the output of the driver
102
is at a constant low level, the output of the CMOS inverter
116
is at a high level and the transmission line termination
105
is in a configuration of being connected to the ground potential through the medium of the n-channel MOS transistor
113
.
If the output signal of the driver
102
rises from a low level to a high level, after a delay time in the transmission line
104
has elapsed, the voltage of the transmission line termination
105
rises from a low level. When the potential of the transmission line termination
105
exceeds a high level threshold value, in response, the output signal of the CMOS inverter
116
switches from a high level to a low level, the termination
105
of the transmission line
104
is connected to the power supply voltage Vcc through the medium of the p-channel MOS transistor
112
, and the potential of the transmission line termination
105
is pulled up by means of the power supply voltage Vcc.
At this time, current temporarily flows to the transmission line termination
105
from the power supply voltage Vcc through the medium of the p-channel MOS transistor
112
, but when the potential of the transmission line termination
105
reaches a high level, current flow stops.
In the condition in which the potential of the transmission line termination
105
is stabilized at a high level, the transmission line termination
105
connected to the power supply voltage Vcc through the medium of the p-channel MOS transistor
112
.
After that, if the driver
102
drops the output signal from a high level to a low level, a reverse operation from the operation explained above is conducted. In other words, the output signal of the CMOS inverter
116
is switched from a low level to a high level, the termination
105
of the transmission line
104
is connected to the ground potential through the medium of the n-channel MOS transistor
113
, and the potential of the transmission line termination
105
is pulled down. At the time of this pulling down, current flows from the transmission line termination
105
to the ground potential side through the medium of the n-channel MOS transistor
113
, and after the potential of the transmission line termination
105
reaches a low level, the current almost ceases to flow.
In this way, in the terminating circuit
111
explained above, when the potential of the transmission line termination
105
is at a high level, the termination
105
is terminated at the power supply potential Vcc, and when it is at a low level, the termination
105
is terminated at the ground potential. When switching the logic level, as explained above, a slight amount of current flows through the transmission line termination
105
, but since current does not flow when the logic level of the transmission line termination
105
is fixed, the power consumption loss can be greatly reduced compared to the case when a resistor is always connected to the transmission line termination.
Also, since the ON resistance of the p-channel MOS transistor
112
of the power supply voltage Vcc side and the ON resistance of the n-channel MOS transistor
113
of the ground potential side are both predetermined so as to match the line impedance of the transmission line
104
, there is no reflection at the transmission line termination
105
, and waveform distortion is not generated.
However, in the above-mentioned terminating circuit
111
, when the logic level is switched, a problem is created wherein a large overshoot and undershoot are generated for the input voltage of the receiver
103
.
A waveform voltage diagram for the output voltage of the above-mentioned driver
102
and the input voltage for the receiver
103
are respectively shown on the curves (X) and (Y) of FIG.
11
.
As shown on curve (X), when the output voltage of the driver
102
rises from a reference voltage (0 V) corresponding to a low level to the reference voltage 3.3 V corresponding to a high level, the input voltage of the receiver
103
also rises from the reference voltage 0 V corresponding to a low level to a high level. When the input voltage for the receiver
103
rises, as is shown on the curve (Y), it rises above the reference voltage 3.3 V corresponding to a high level and reaches almost 4.5 V, so it can be seen that a large overshoot is generated.
In the same manner, when the output voltage of the driver
102
drops from a reference voltage 3.3 V corresponding to a high level to a reference voltage (0 V) corresponding to a low level, as is shown on the curve (Y), the input voltage for the receiver
103
drops lower than the reference voltage (0 V) corresponding to the low level and almost reaches −1.2 V, so it can be seen that a large undershoot is generated.
This invention was achieved for the purpose of solving the unfavorable behavior of the above-mentioned prior technology, and its objective is to offer a terminating circuit that can either eliminate or reduce the overshoot and the undershoot that are generated at th
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tokar Michael
Tran Anh
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