Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-06-20
2006-06-20
Le, Don (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000
Reexamination Certificate
active
07064576
ABSTRACT:
Techniques for reducing the leakage currents through on-chip impedance termination circuits are provided. An on-chip impedance termination circuit includes a network of resistors and transistors formed on an integrated circuit. The termination circuit is coupled to one or more IO pins. The transistors can be turned ON and OFF to couple or decouple subsets of the resistors from the IO pins. The bodies of transistors305–306are coupled to a supply voltage to cut off leakage current. By pulling the body of these transistors to a supply voltage, the transistor's drain/source-to-body diodes turn OFF preventing unwanted leakage current. Also, by moving the source/drain/body node of transistors301–304to Node2, leakage currents through transistors301–304are eliminated.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 4954729 (1990-09-01), Urai
patent: 5111081 (1992-05-01), Atallah
patent: 5134311 (1992-07-01), Biber et al.
patent: 5164663 (1992-11-01), Alcorn
patent: 5179300 (1993-01-01), Rolandi et al.
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5592510 (1997-01-01), Van Brunt et al.
patent: 5602494 (1997-02-01), Sundstrom
patent: 5623216 (1997-04-01), Penza et al.
patent: 5726582 (1998-03-01), Hedberg
patent: 5726583 (1998-03-01), Kaplinsky
patent: 5764080 (1998-06-01), Huang et al.
patent: 5864715 (1999-01-01), Zani et al.
patent: 5939896 (1999-08-01), Hedberg
patent: 5955911 (1999-09-01), Drost et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6008665 (1999-12-01), Kalb et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6037798 (2000-03-01), Hedberg
patent: 6049255 (2000-04-01), Hagberg et al.
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6097208 (2000-08-01), Okajima et al.
patent: 6100713 (2000-08-01), Kalb et al.
patent: 6118310 (2000-09-01), Esch, Jr.
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: 6154060 (2000-11-01), Morriss
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6181157 (2001-01-01), Fiedler
patent: 6236231 (2001-05-01), Nguyen
patent: 6252419 (2001-06-01), Sung et al.
patent: 6329836 (2001-12-01), Drost et al.
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6411126 (2002-06-01), Tinsley et al.
patent: 6414512 (2002-07-01), Moyer
patent: 6424169 (2002-07-01), Partow et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6448813 (2002-09-01), Garlepp et al.
patent: 6466063 (2002-10-01), Chen
patent: 6489837 (2002-12-01), Schultz et al.
patent: 6504397 (2003-01-01), Hart et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6639397 (2003-10-01), Roth et al.
patent: 6642741 (2003-11-01), Metz et al.
patent: 6686772 (2004-02-01), Li et al.
patent: 6710618 (2004-03-01), Murray
patent: 6766155 (2004-07-01), Salcido et al.
patent: 6815980 (2004-11-01), Kerr
patent: 6859064 (2005-02-01), Maangat
patent: 2002/0010853 (2002-01-01), Trimberger et al.
patent: 2002/0060602 (2002-05-01), Ghia et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 2003/0062922 (2003-04-01), Douglass et al.
patent: 2004/0008054 (2004-01-01), Lesea et al.
Altera, Apex 20K “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Altera, Apex II “Programmable Logic Device Family,”Altera Corporation, Ver. 1.1, May 2001.
Bendak, M. et al. (1996). “CMOS VLSI Implementation of Gigabyte/second computer network links,” Dept. of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0407, IEEE International Symposium on Circuits and Systems pp. 269-272, no month.
Boni, A. et al. (2001). “LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-um CMOS,” IEEE Journal of Solid-State Circuits, 38(4):706-711, no month.
Esch and Manley, Theory and Design of CMOS HSTL I/O Pads, The Hewlett Packard Journal, Aug. 1998.
Xilinx, “Spartan-3 1.2V FPGA Family: Functional Description,” Xilinx, DS099-2 (v1.2) Jul. 11, 2003.
Xilinx, “Virtex-II 1.5V Field Programmable Gate Arrays,” Xilinx, DSO3102 (v1.5), Apr. 2, 2001.
Xilinx, “Virtex-II Platform FPGAs: Detailed Description,” Xilinx, DS031-2 (v3.1) Oct. 14, 2003.
Xilinx, “Virtex-II Pro Platform FPGAs: Functional Description,” Xilinx, DS083-2 (v2.9) Oct. 14, 2003.
Altera Corporation
Le Don
Townsend and Townsend / and Crew LLP
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