Source synchronous I/O using temporal delay queues
Source synchronous interface using variable digital data...
Source-coupled logic with reference controlled inputs
Spare cell architecture for fixing design errors in...
Spatially filtered data bus drivers and receivers and method...
Specialized programmable logic region with low-power mode
Specialized programmable logic region with low-power mode
Specialized programmable logic region with low-power mode
Speed enhanced level shifting circuit utilizing diode capacitanc
Speedpath repair in an integrated circuit
Spike-triggered asynchronous finite state machine
Spin-orbital quantum cellular automata logic devices and...
Split FIFO configuration of block RAM
SR-flip flop with level shift function
SSTL voltage translator with dynamic biasing
Stacked buffers
Staged predriver for high speed differential transmitter
Staggered I/O groups for integrated circuits
Staggered output circuit for noise reduction
State machine and system and method of implementing a state...