Source synchronous I/O using temporal delay queues

Details Source synchronous I/O using temporal delay queues Source synchronous I/O using temporal delay queues

2002-03-26

2004-03-02

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S040000, C326S046000, C365S189011, C365S221000, C365S230020

Reexamination Certificate

active

06700409

ABSTRACT:

BACKGROUND OF INVENTION
In digital systems, data is transmitted between circuit elements. The transmission and reception of data is based on a system clock. The system clock maintains a known time reference to synchronize the activities of the digital system. In a synchronous system, data is expected to arrive at a receiver within a known number of cycles. The number of cycles needed for the data transmission is commonly referred to as “latency”.
The system clock may have to route to many circuits elements that have different delays from the source of the system clock. The system clock that is local to a circuit element may be skewed with respect to the system clock that is local to another circuit element. Also, depending on the transmission path, the delay to transmit the data from one circuit element to another may vary. Accordingly, the data from a transmitting circuit element may not consistently arrive within the same clock cycle at a receiver. If the arrival of the data is close to a boundary of a clock cycle, the data may intermittently arrive at different clock latencies due to variations in an operating environment such as temperature, voltage, and/or system noise.
Because latency varies, source synchronous arrangements are often used. With source synchronous transmission, a clock is transmitted with the data to indicate when the receiver should latch the data. The clock edge often transitions near the beginning of when the data is valid. With a source synchronous arrangement, both the data and its associated clock experience similar delays; therefore, the receiver has an appropriate indicator of when the data should be latched.
FIG. 1
a
shows a section of a computer system (
100
). The section of the computer system (
100
) may be representative of circuits on a single integrated circuit, or representative of multiple integrated circuits. Circuit element one (
102
) and circuit element two (
104
) may transmit data to circuit element three (
106
). A local system clock (
111
) relative to circuit element one (
102
) and a local system clock (
113
) relative to circuit element two (
104
) and circuit element three (
106
) are skewed with respect to a system clock (
109
). Clock skew is a result of different delays imposed on various sections of the system clock (
109
) routing due to different parasitics, such as impedance network Z
A
(
108
) and impedance network Z
B
(
110
).
Circuit element one (
102
) and circuit element two (
104
) transmit data on the rising edge of their respective local system clocks (
111
,
113
) during the system clock (
109
) cycle indicated by “CYCLE N” in the timing diagram of
FIG. 1
b
. Also, send_clk1 (
103
) and send_clk2 (
107
) transition similarly to local system clocks (
111
,
113
), respectively. Send_clk1(
103
) and send_clk2 (
107
) provide a source synchronous latching signal to the receivers in circuit element three (
106
). The transmission delay caused by impedance network Z
c
(
120
) from circuit element one (
102
) to circuit element three (
106
) causes the data to arrive after the reception of data from circuit element two (
104
). The impedance network Z
D
(
122
) causes a reduced delay compared to impedance network Z
C
(
120
). The data from circuit element one (
102
) and circuit element two (
104
) arrive within different clock cycles at circuit element three (
106
). Shown in
FIG. 1
b
, both transmissions take longer than a single clock cycle to propagate to their destination and each has a different arrival time relative to the local system clock (
113
) cycle boundaries.
In
FIG. 1
b
, the reception of data from circuit element one (
102
) at circuit element three (
106
) occurs near a clock cycle boundary of the local system clock (
113
) of circuit element three (
106
). Depending on variations in the operating environment, the data transmitted from circuit element one (
102
) may be received with different latencies.
SUMMARY OF INVENTION
According to one aspect of the present invention, a temporal delay circuit for synchronizing a source synchronous input comprises a data input and a source synchronous clock with a local clock, comprises a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.
According to one aspect of the present invention, a method for synchronizing a source synchronous input with a local clock, where the source synchronous input comprises a data input and a source synchronous clock, the method comprises using a temporal delay queue to store the data input based on the source synchronous clock, using a write pointer to determine where to store the data input in the temporal delay queue where the write pointer is based on the source synchronous clock, and using a read pointer to determine a location in the temporal delay queue from which the data input should be read where the read pointer is in phase with the local clock and arranged to read from the temporal delay queue according to a desired delay.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5901100 (1999-05-01), Taylor
patent: 6327207 (2001-12-01), Sluiter et al.

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