Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-01-23
2003-12-02
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000, C326S024000, C326S027000, C333S103000
Reexamination Certificate
active
06657460
ABSTRACT:
FIELD OF INVENTION
The present invention generally relates to microelectronic devices. More particularly, the present invention relates to bus drivers and receivers with improved signal integrity.
BACKGROUND OF THE INVENTION
In digital systems, data is typically represented by a group of bits representing the value of that data, where the bit value is typically a logical high or a logical low. A logical high level is typically represented by a high-voltage level, such as that of the positive power supply, and a logical low level is typically represented by a low-voltage level, such as that of the device ground.
The processing of digital data typically involves transmitting signals representing individual bits from one digital block or subsystem to another digital block or subsystem. Since the representation of data contains of multiple bits (such as 8-bit words or 16-bit words), a digital bus typically transmits a parallel set of bits from one physical location to another using multiple traces.
In a typical digital system, the timing of the system may be critical. The signals are typically configured to recognize transitions between logical levels only at particular times. In addition, the voltage levels of the system may also be critical. For example, if 0 volts represents a logical low signal and 3.3 volts represents a logical high signal, a voltage level outside of predetermined voltage tolerances is ambiguous (e.g., it may not be possible to determine whether a voltage level of 1.6 volts represents a logical low or a logical high level.)
FIG. 1
illustrates a typical data bus where eight digital bits are transmitted from one location, represented by signals
101
-
108
, to another location, represented by signals
111
-
118
. The medium for transmission in
FIG. 1
is an 8-bit bus having traces (
121
-
128
). In order to transmit the signal over the bus, drivers
131
-
138
are used to generate the proper signals to send via bus
121
-
128
, and receivers
141
-
148
are used to detect the signal on the bus to generate the appropriate digital signals
111
-
118
.
While the data bus has been described as taking the form of traces
121
-
128
, the bus may take one of several different forms, such as traces on an integrated circuit, on a hybrid or package, a printed circuit board, a ribbon cable, or a backplane, depending on the location of the digital blocks or subsystems. Furthermore, the data bus may consist of a single destination and set of receivers or multiple destinations and sets of receivers.
Drivers
131
-
138
may include buffers (non-inverting) or inverters. Similarly, receivers
141
-
148
may consist of buffers or inverters, and digital signals
111
-
118
, the respective outputs from receivers
141
-
148
, may consist of an equivalent data representation of signals
101
-
108
.
When a digital signal (representing the value of a single bit) switches from low to high, it may affect the signal on traces in physical proximity. Such spatial effects may include crosstalk, wherein the signal on one trace is coupled to the signal on another trace, or ground or supply bounce, wherein the voltage at ground and the power supply is not maintained at a relatively constant value due to the current flow used to effect the switching.
FIG. 2
illustrates a 2-dimensional cross-section of a typical 8-bit data bus. The data bus includes traces
201
-
208
. The electrical characteristics of the bus depend on the physical dimensions of the traces (including the width, height, and spacing of the traces), the distance from the traces to a ground plane
209
, and the characteristics of the dielectric material
210
which surrounds the traces. As noted above, the data bus may take various forms, such as traces on an integrated circuit, on a hybrid or package, a printed circuit board, a ribbon cable, or a backplane. However, for purposes of
FIG. 2
, they will be referred to as traces.
For typical chip and board interconnects, the electrical characteristics of the bus are dominated by the parasitic capacitance of the traces. Parasitic capacitance is the undesired capacitance that may result from the physical proximity of two electrical conductors. The parasitic capacitance may result from the proximity of a signal trace (
201
-
208
) to ground (
209
), as represented by parasitic capacitances
211
-
219
, or from the proximity of one trace (
201
-
208
) to another trace (
201
-
208
), as represented by parasitic capacitances
221
-
227
. There may also be additional parasitic capacitances due to other signal traces such as
231
-
233
, represented by parasitic capacitances
234
-
237
. For well-designed buses, however, the placement of traces
201
-
208
is often configured such that parasitic capacitances
231
-
233
are much less significant than the parasitic capacitance to ground (
211
-
219
) and the parasitic capacitance between traces (
221
-
227
).
FIG. 3
illustrates a three-dimensional view of a 3-bit bus with signal traces
301
-
303
and ground plane
304
, similar to the 8-bit bus cross-section shown in FIG.
2
.
FIG. 3
illustrates that the length of the traces on a bus has an effect on the magnitude of the parasitic capacitances to ground and between traces, as the longer the traces are, the more area for which a capacitance to form. In general, the parasitic capacitances are proportional to the length of a trace, such that long buses have higher parasitic capacitance, but the relative ratio of those values are mostly dependent on the cross-sectional spacing.
Through the parasitic capacitance and inductance, the waveform on a signal trace will have an effect on adjacent traces; thus, the traces on the bus do not behave independently, but may be at least partially dependent on the signal waveforms on all traces. More particularly, a change in voltage or current in a trace can affect an adjacent trace through the parasitic capacitance and mutual inductance coupling. For simplification, the dominant terms for each trace can be considered for most practical cases to be the parasitic capacitance to ground and the parasitic capacitances to immediately adjacent traces, and the bus can be thought of consisting of a multiple port network or spatial filter.
The coupling results in undesirable deviations, such as crosstalk, to the waveform at the receiver such that the maximum operating frequency of the signals is typically limited for successful transmission and reception over the bus. Operating frequencies faster than the maximum operating frequency may result in difficulty in determining the proper state (logical high or logical low) of the various bits.
In addition, the current drawn by the buffers during signal transitions will vary depending on the number of signals transitioning simultaneously in the same direction, such as from logical-low to logical-high. This change in current leads to a variation in the voltage supply or the ground, resulting in a change in the signal waveforms, known as ground bounce.
When several devices are nearly simultaneously (i.e., during the same computing clock period) transitioning from a logical-low to a logical-high, and several other devices are also transitioning from a logical-high to a logical-low, the ground bounce presented is minimal, as the opposite switching directions of the devices may tend to cancel each other out, whereas when most signals transition in the same direction, the ground bounce is greater. Furthermore, when adjacent signals switch in opposite directions, coupling due to crosstalk is increased, resulting in smaller amplitudes and degraded transition times, making it more difficult to determine the correct state for each particular signal.
With reference to
FIG. 8
, several exemplary waveforms showing the possible effect of crosstalk and ground bounce are presented. In
FIG. 8
, an 8-bit bus (such as the one illustrated in
FIG. 1
) is modeled as a multiple-port network. The supply voltage and ground are modeled as series resistance and inductance in order to account for ground bounce.
The input waveform
801
is app
Chang Daniel
Galanthay Theodore E.
Primarion, Inc.
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