Source synchronous interface using variable digital data...

Details Source synchronous interface using variable digital data... Source synchronous interface using variable digital data...

2002-09-11

2004-09-14

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S096000, C327S149000

Reexamination Certificate

active

06791360

ABSTRACT:

BACKGROUND OF THE INVENTION
As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, source synchronous transmission may be used in which a clock signal is transmitted to help recover the data. The clock signal determines when the data signal should be sampled by a receiver's circuits.
The clock signal may transition at the beginning of the time the data signal is valid. The receiver often requires, however, that the clock signal transition during the middle of the time that the data signal is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission source. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase offset from the original clock signal.
A DLL must generate a copy of the clock signal with a known phase offset relative to the clock signal input into the DLL. A single cycle of a clock signal is considered to occur over 360 degrees. By specifying a phase offset, the same relative temporal delay is specified; however, the absolute amount of temporal delay may be different. For example, a 100 MHz clock signal has a 10 ns cycle time; therefore, a phase offset of 360 degrees would indicate that an entire cycle, or 10 ns, of delay has been added. A ninety degree phase offset is 2.5 ns (i.e., one fourth of the entire cycle). A 200 MHz clock signal has a cycle time of 5 ns. A ninety degree phase offset in this case is only 1.25 ns. The phase offsets in these examples are the same; however, the temporal delays are not.
FIG. 1
shows a typical source synchronous communication system (
100
). Data signals that are “K” bits wide are transmitted from circuit A (
12
) to circuit B (
34
) on a data path (
14
). To aid in the recovery of the transmitted data signals, a clock signal is transmitted on a clock path (
16
) at a similar time as the data signal. Although not shown, the communication system (
100
) could also have a path to transmit data signals from circuit B (
34
) to circuit A (
12
) along with an additional clock signal (not shown).
In
FIG. 1
, a DLL (
40
) generates a copy of the clock signal on the clock path (
16
) with a valid state and with a phase offset to be used by other circuits. For example, the DLL (
40
) outputs the copy of the clock signal with a predetermined phase offset to cause a latch device to sample the data signal. A latch device may be, for example, a flip-flop (
38
) as shown in FIG.
1
. When the copy of the clock signal transitions, the flip-flop (
38
) samples the output of an amplifier (
36
) that amplifies the data signal on the data path (
14
). The latched signal from the flip-flop (
38
) is provided to other circuits on circuit B (
34
) as a local data signal (
42
).
The DLL (
40
) is arranged to maintain a constant phase offset between the clock signal input to the DLL (
40
) and the clock signal output from the DLL (
40
). The clock signal input to the DLL (
40
) may jitter. In other words, the clock signal may transition at relative intervals that are not equally spaced in time. Jitter in the transmitted clock signal degrades the performance of the source synchronous communication system (
100
).
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a communication system comprises a first clock path arranged to carry a clock signal; a second clock path arranged to carry a local clock signal; a data path arranged to carry a data signal; a digital delay line arranged to delay the data signal to produce a delayed data signal; and a delay locked loop arranged to operatively control the delay of the digital delay line dependent on the clock signal and the local clock signal.
According to one aspect, a method for performing source synchronous interface operations comprises transmitting a clock signal; transmitting a local clock signal; transmitting a data signal; delaying the data signal using a digital delay line to produce a delayed data signal; and controlling the delaying dependent on the clock signal and the local clock signal.
According to one aspect, a communication system comprises means for transmitting a clock signal; means for transmitting a local clock signal; means for transmitting a data signal; means for delaying the data signal to produce a delayed data signal; means for controlling the delaying dependent on the clock signal and the local clock signal; and means for periodically updating the means for delaying.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5636254 (1997-06-01), Hase et al.
patent: 6333657 (2001-12-01), Okajima
patent: 6373313 (2002-04-01), Hishiyama
patent: 6549041 (2003-04-01), Waldrop
PCT International Search Report for PCT/US 03/24635 dated Nov. 28, 2003 (3 pages).
“A Semidigital Dual Delay-Locked Loop” as published in the IEEE Journal of Solid-State Circuits vol. 32, No. 11 (5 pages) Authors: Stefanos Sidiropoulos and Mark A. Horowitz Manuscript submitted Apr. 10, 1997; Revised Jun. 5, 1997.
“A Semidigital Dual Delay-Locked Loop”; by Stefanos Sidiropoulos and Mark A. Horowitz, IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997 (10 pages).

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