I/O buffer circuit with pin multiplexing

I/O cell architecture for CPLDs

I/O cell configuration for multiple I/O standards

I/O cell configuration for multiple I/O standards

I/O circuitry shared between processor and programmable...

I/O circuitry shared between processor and programmable...

I/O circuitry shared between processor and programmable...

I/O interface cell for use with optional pad

I/O transceiver having a pulsed latch receiver circuit

IC chip using a common multiplexor logic element for performing

IC having programmable digital logic cells

IC output signal path with switch, bus holder, and buffer

IC with digital and analog circuits and mixed signal I/O pins

IC with digital and analog circuits and mixed signal I/O pins

IC with dual input output memory buffer

Implementation of high speed synchronous state machines with sho

Implementing a priority function using ripple chain logic

Implementing complex clock designs in field programmable...

Implementing conditional statements in self-timed logic...

Implementing wide multiplexers in an FPGA using a horizontal...