Six-input look-up table for use in a field programmable gate...
Skipping clock interrupts during system inactivity to reduce pow
Slew rate selection circuit for a programmable device
Soft core control of dedicated memory interface hardware in...
Soft core control of dedicated memory interface hardware in...
Soft core control of dedicated memory interface hardware in...
Software programmable logic using spin transfer torque...
Software programmable logic using spin transfer torque...
Spare cell architecture for fixing design errors in...
Specialized programmable logic region with low-power mode
Specialized programmable logic region with low-power mode
Specialized programmable logic region with low-power mode
Spike-triggered asynchronous finite state machine
Split FIFO configuration of block RAM
Staggered I/O groups for integrated circuits
State machine and system and method of implementing a state...
State machine in a programmable logic device
State machines using non-volatile re-writeable two-terminal...
State machines using resistivity-sensitive memories
State saving and restoration in reprogrammable FPGAs